Managing contention for shared resources on multicore processors
نویسندگان
چکیده
منابع مشابه
Shared Memory Abstractions for Heterogeneous Multicore Processors
We are now seeing diminishing returns from classic single-core processor designs, yet the number of transistors available for a processor is still increasing. Processor architects are therefore experimenting with a variety of multicore processor designs. Heterogeneous multicore processors with Explicitly Managed Memory (EMM) hierarchies are one such experimental design which has the potential f...
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Multicore processors allow manufacturers to integrate larger numbers of simpler processing cores onto the same chip with few or no changes to the processing core architecture. These processors can simultaneously execute threads from separate processes (multiprogrammed workloads) or from the same multi-threaded application (parallel workloads). The design space for on-chip memory hierarchies inc...
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The computer industry is undergoing a momentous transformation. General-purpose computing is moving off of desktops and onto diverse device such as smart phones, digital entertainment centers, and data center servers. At the same time, high-performance semiconductor manufacturers are continuing the long-term trend of increasing integration and are now manufacturing multicore chips. It is our po...
متن کاملContention in Multicore Hardware Shared Resources: Understanding of the State of the Art
The real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been accentuated with the arrival of multicore processors. From the state of the art on the subject, there appears to be considerable diversity in the understanding of the problem...
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The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction a...
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ژورنال
عنوان ژورنال: Communications of the ACM
سال: 2010
ISSN: 0001-0782,1557-7317
DOI: 10.1145/1646353.1646371